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IXBD4410 IXBD4411
ISOSMARTTM Half Bridge Driver Chipset
Type Description Package Temperature Range
IXBD4410PI IXBD4411PI IXBD4410SI IXBD4411SI
Full-Feature Low-Side Driver 16-Pin P-DIP Full-Feature High-Side Driver 16-Pin P-DIP Full-Feature Low-Side Driver 16-Pin SO Full-Feature High-Side Driver 16-Pin SO
-40 to +85C -40 to +85C -40 to +85C -40 to +85C
The IXBD4410/IXBD4411 ISOSMART chipset is designed to control the gates of two Power MOSFETs or Power IGBTs that are connected in a halfbridge (phase-leg) configuration for driving multiple-phase motors, or used in applications that require half-bridge power circuits. The IXBD4410/ IXBD4411 is a full-feature chipset consisting of two 16-Pin DIP or SO devices interfaced and isolated by two small-signal ferrite pulse transformers. The small-signal transformers provide greater than 1200 V isolation. Even with commutating noise ambients greater than 50 V/ns and up to 1200 V potentials, this chipset establishes error-free two-way communications between the system ground-reference IXBD4410 and the inverter output-
reference IXBD4411. They incorporate undervoltage VDD or VEE lockout and overcurrent or desaturation shutdown to protect the IGBT or Power MOSFET devices from damage. The chipset provides the necessary gate drive signals to fully control the grounded-source low-side power device as well as the floating-source high-side power device. Additionally, the IXBD4410/4411 chipset provides a negative-going, off-state gate drive signal for improved turn-off of IGBTs or Power MOSFETs and a system logiccompatible status fault output FLT to indicate overcurrent or desaturation, and undervoltage VDD or VEE. During a status fault, both chipset keep their respective gate drive outputs off; at VEE.
Features 1200 V or greater low-to-high side isolation. Drives Power Systems Operating on up to 575 V AC mains dv/dt immunity of greater than 50V/ns Proprietary low-to-high side level translation and communication On-chip negative gate-drive supply to ensure Power MOSFET or IGBT turn-off and to prevent gate noise interference 5 V logic compatible HCMOS inputs with hysteresis Available in either the 16-Pin DIP or the 16-Pin wide-body, small-outline plastic package 20 ns switching time with 1000 pF load; 100 ns switching time with 10,000 pF load 100 ns propagation delay time 2 A peak output drive capability Self shut-down of output in response to over-current or short-circuit Under-voltage and over-voltage VDD lockout protection Protection from cross conduction of the half bridge Logic compatible fault indication from both low and high-side driver Applications
540 V-
1- or 3-Phase Motor Controls Switch Mode Power Supplies (SMPS) Uninterruptible Power Supplies (UPS) Induction Heating and Welding Systems Switching Amplifiers General Power Conversion Circuits
IXYS reserves the right to change limits, test conditions and dimensions.
(c) 2004 IXYS All rights reserved
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IXBD4410 IXBD4411
Symbol VDD/VEE Vin Iin Io (rev) PD PD TA TJM Tstg TL RthJA RthJC Definition Supply Voltage Input Voltage (INH, INL) Input Current (INL, INH, IM) Peak Reverse Output Current (OUT) Maximum Power Dissipation (TA = 25 C) TC = 25 C (16-Pin SOIC) Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Range Lead Soldering Temperature for 10 s (16-Pin SOIC) Maximum Ratings -0.5 ... 24 -0.5...VDD +0.5 10 2 600 10 -40 ... 85 150 -55 ... 150 300 1.67 10 V V A A mW W C C C C K/W K/W
Die substrate connected to tab
Dimensions in inch (1" = 25.4 mm) 16-Pin SOIC
Recommended Operating Conditions VDD/VEE VDD/LG LGh/LGl Symbol Supply Voltage Maximum Common Mode dv/dt 10 ... 20 V 10 ... 16.5 V 50 V/ns
Definition/Condition Characteristic Values (TA = 25C, VDD = 15 V, unless otherwise specified) min. typ. max.
INL, INH Inputs (referred to LG) Vt+ VtVih Iin Cin Positive-Going Threshold Negative-Going Threshold Input Hysteresis Input Leakage Current/Vin=VDD or LG Input Capacitance 3.65 1 1 -1 10 1 V V V A pF
16-Pin Plastic DIP
Open Drain Fault Output (referred to LG) Voh Vol HI Output/Rpu = 10 k to VDD LO Output/Io = 4 mA VDD-0.05 0.3 0.5 V V
OUT Output (referred to LG) Voh Vol Ro Ro Ipk HI Output/Io = -5 mA LO Output/Io = 5 mA Output HI Res./Io = -0.1 A Output LO Res./Io = 0.1 A Peak Output Current/CL = 10 nF VDD-0.05 VEE+0.05 3 3 2 V V A End view
5 4
1.5
IM Input (referred to KG) Vt+ Cin Rs Positive-Going Threshold Input Capacitance Shorting Device Output Resistance 0.24 50 0.3 10 75 0.45 100 V pF
VEE Supply (referred to LG) VEE Iout finv VEEF Output Voltage/Io = 1 mA, Co = 1 F Output Current/Vout = 0.70 * VEE Inverting Frequency Undervoltage Fault Indication -5 -20 -3 -6.5 -25 600 -7.5 V mA kHz V
-4.8
(c) 2004 IXYS All rights reserved
IXBD4410 IXBD4411
Symbol Definition/Condition Characteristic Values (TA = 25C, VDD = 15 V, unless otherwise specified) min. typ. max.
VDD Undervoltage Lockout Vuv Vuh Drop Out Hysteresis 9.5 0.1 10.5 0.15 11.5 0.3 V V
Quiescent Power Supply Current IDD VDD Current/Vin=VDD or LG, Io = 0 20 mA
INL and INH Inputs (Fig. 1a - 1c) td(on) tr td(off) tf tdlh(off) Turn-on delay time; 4410 Rise time; Turn-off delay time 4410 Fall time 4410/4412 Turn-on delay time vs. 4411 Turn-off delay time tdlh(on) 4410 Turn-on delay time vs. 4411 Turn-off delay time CL =1nF 60 150 ns CL =1nF 60 150 ns CL =1nF CL =10 nF CL =1 nF CL =1nF CL =10nF CL =1nF 110 70 15 70 70 15 175 100 20 150 150 20 ns ns ns ns ns ns
Fault Output Delay for any Fault Conditions (4410/4411) tFLT FLT Delay/Rpu = 2 k CL = 20 pF 200 300 ns
Overcurrent Protection Delay toc Driver-Off delay time CL = 1 nF 200 300 ns
1N5817
1N5817
Fig. 1a: IXBD4410/4411 Switching time test circuit (c) 2004 IXYS All rights reserved
Fig. 1b: Output signal waveform
3
IXBD4410 IXBD4411
Chipset Overview
This ISOSMARTTM chipset is a pair of integrated circuits providing isolated high- and low-side drivers for phaseleg motor controls, or any other application which utilizes a half bridge, 2- or 3-phase drive configuration. They consist of two drive control inputs (INL and INH) for two Power-MOSFET/IGBT gate-drive outputs. Both inputs operate from a common ground and are activated by HCMOS compatible logic levels. The low-side output operates near input ground, while the high-side output operates from a floating ground that is nominally the source connection of the high-side phase-leg power device. Both outputs typically provide 2 A of transient current drive for fast switching of the phase-leg power device. IXBD4410/IXBD4411 The full featured ISOSMARTTM driver chipset incorporates a IXBD4410 as the low-side driver (Fig. 3) and a IXBD4411 as the high-side driver (Fig. 2). When input "INL" is set to a positive logic level, the low-side gate output goes high (turns on); when "INH" is set to a positive logic level, the high-side gate drive output goes high. The highside IC is isolated from the low-side IC by a magnetic barrier, across which the turn on/off signal is transmitted to the high-side gate drive. The IXBD4411 fault signal is also transmitted back to the IXBD4410 driver via these transformers. This isolation only depends on the low cost communications transformer, which is designed to withstand 1200 V or more. There are two magnetic transmission channels between the low- and highside IC's for bi-directional communication. One sends a signal from the low-side IXBD4410 IC up to the highside IXBD4411 IC and the other sends a signal back from the high-side to the low-side IC. The signal that is sent up controls the IXBD4411 gate-drive output. The signal sent from the IXBD4411 back to the IXBD4410 indicates a high-side fault has occurred (overcurrent, or under-voltage of the high-side +power supplies). This is detected at the IXBD4410 driver and sets "FLT" pin low, to indicate the highside fault. The fault signal that is returned from
15
VDD
UVDD UVEE
14
VEE
13 12
Fig. 2: IXBD4411, high-side driver block diagram
15
VDD
UVDD UVEE
14
VEE
13 12
Fig. 3: IXBD4410, low-side driver block diagram
Fig. 4: Logic representation of IXBD4410 FLT signal (c) 2004 IXYS All rights reserved
IXBD4410 IXBD4411
the IXBD4411 is strictly for status only. Any gate-drive shutdown because of a high-side fault is done locally within the
high-side IXBD4411. The IXBD4411 gate-drive will turn-off the power device whenever an overcurrent or under voltage condition arises. The overcurrent sensing is active only while the gate driver output is "high" (on). The overcurrent fault condition is latched and is reset on the next INH gate input positive transition. The FLT (pin 8) of the IXBD4411 is not used and should be grounded. The low-side IXBD4410 driver provides an output pin 8 (FLT) to indicate a highside (IXBD4411) or a low-side (IXBD4410) fault. This output pin is an "open-drain" output. The IXBD4410 lowside driver fault indications are similar to the IXBD4411 high-side driver indications as outlined above. A "graphic" logic diagram of the chipset's FLT function is presented in Fig.4. Note that this diagram presents the logic of this function at the "low-side" IXBD4410 driver and is not the actual circuit. It describes the combined logic of the "fault logic" and "hi-side fault sense" blocks in both the IXBD4410 and IXBD4411 as shown in Fig. 2 and 3. The most efficient method of providing power for the high-side driver is by bootstrapping. This method is illustrated in the functional drawing on page 4 and in the application example (Fig. 6 and 9) by diode D1 and capacitor C1. Using this method, the power is drawn through a high-voltage diode onto a reservoir capacitor whenever the floating high-side ground returns to near the real ground of the low-side driver. When the high-side gate is turned on and the floating ground moves towards a higher potential, the bootstrapping diode back-biases, and the high-side driver draws its power solely from the reservoir capacitor. Power may also be provided via any isolated power supply (usually an extra secondary on the system housekeeping supply switching transformer). Both the IXBD4410 and IXBD4411 contain on-board negative charge pumps to provide negative gate drive, which ensures turn-off of the high- or low-side power device in the presence of currents induced by power device Miller capacitance or from inductive ground transients. These charge pumps provide -5 V relative to the local driver ground when VDD is at +15 V, and at rated average currents of 25 mA. The charge pump requires two external capacitors, C7 and C11 in Fig. 6. The charge pump frequency is nominally 600 kHz. The charge pump clock is turned off whenever the difference between the VDD and VEE supplies exceed 20 V, to prevent exceeding the breakdown rating of the IC. Both the IXBD4410 and IXBD4411 drivers possess two local grounds each, a common logic ground, and "Kelvin" ground. The Kelvin ground and logic grounds are first connected directly to each other, and then to the Kelvin-source of the power device for accurate overcurrent measurement in the presence of inductive transients on the power device source terminal. Power MOSFET or IGBT overcurrent sensing utilizes an on-chip comparator with a typical 300 mV threshold. In a typical application, the current mirror pin of the Power MOSFET or IGBT is connected to a grounded, low-value resistor, and to the overcurrent comparator input on the high- or low-side driver. The comparator will respond typically within 150 ns to an overcurrent condition to shutdown the driver output. The power switches could be protected also by desa-turation detection (see Fig. 6, 7 and 9). To assure maximum protection for the phase-leg power devices, the chipset incorporates the following Power MOSFET and IGBT protection circuits: Power device overcurrent or desaturation protection. The IXBD4410/ 4411will turn off the driven device within 150 ns of sensing an output overcurrent or desaturation condition. Gate-drive lockout circuitry to prevent cross conduction (simultaneous conduction of the low- and high-side phase-leg power devices), either under normal operating conditions or when a fault occurs. During power-up, the chipset's gatedrive outputs will be low (off), until the voltage reaches the under-voltage trip point. Under-voltage gate-drive lockout on the low- and/or high- side driver whenever the respective positive power supply falls below 9.5 V typically. Under-voltage gate-drive lockout on the low- and high- side driver whenever the respective negative power supply rises above -3 V typically.
(c) 2004 IXYS All rights reserved
5
IXBD4410 IXBD4411
Pin Description IXBD4410 (Low-Side Driver) Pin Description IXBD4411 (High-Side Driver)
VDD NC NC TT+ RR+ NC VDD OUT VEE CA CB LG KG IM
Sym. Pin Description of IXBD 4410/4411 VDD 1 Positive power supply. 16 INL NC 2 Logic input signal referenced to LG (logic ground). In the IXBD4410. A "high" to this pin turns on its gate drive output and resets its fault logic. A "low" to this pin turns off the gate drive output. In the IXBD4411 this pin is not used and should be connected to its ground (LG). No Connection (IXBD 4411) Logic input signal referenced to LG (logic ground). In the IXBD4410, this signal is transmitted to the IXBD4411 "high-side" driver through pins 4 and 5 (T- and T+). A "high" to this pin turns on the IXBD4411 gate drive output and resets its fault logic. A "low" to this pin turns off the IXBD4411 gate drive output. In the IXBD4411 this pin is not used and should be connected to its ground (LG). No Connection (IXBD 4411) Transmitter output complementary drive signals. Direct drive of the low signal transformer, which is connected to the receiver of the chipset's companion device. In the IXBD4410, this signal transmits the on/off command to its companion IXBD4411. In the IXBD4411, this signal transmits the fault indication to its companion IXBD4410 driver. Receiver input complementary signal. Directly connected to the low signal transformer, which is driven by the chipset's companion device. In the IXBD4410, this input receives the fault indication from its companion IXBD4411 driver. In the IXBD4411, this input receives the on/off command from its companion IXBD4410 driver.
Sym. Pin Description of IXBD 4410/4411 FLT NC 8 Low/high side fault output. In the IXBD4410, this output indicates a fault condition of either device of the chipset. A "high" indicates no fault, A "low" indicates that either overcurrent,VDD or VEE under-voltage occurred. In case of overcurrent, this output will remain active "low" until the next input cycle of the respective driver. In case of under-voltage, this output will remain "low" until the proper voltage is restored. The IXBD4411 does not have a FLT output,and its pin 8 should be tied to LG No Connection (IXBD 4411) Current sense or desaturation detection input. This input is active only while the OUT pin is "high" (on). When the OUT pin is "low" (off) this input is pulled to ground through a 70 resistor. Any voltage at this pin above the threshold of .3 V typical, will turn the output (pin 15) off. This pin is used for power device overcurrent protection.
INH NC
3
IM
9
TT+
4 5
KG
10 Kelvin ground. This ground is used as Kelvin connection for overcurrent or desaturation sensing. 11 Logic and power ground. 12 Capacitor terminals for negative charge pump (VEE); "+" 13 terminal is CB (pin 12).
LG CB CA
RR+
6 7
VEE 14 Negative supply terminal(substrate) OUT 15 Gate drive output. In the IXBD4410 this output responds to the INL signal. A "high" at INL will turn it on ("high"), a "low" will turn it off ("low"). In the IXBD4411, this output responds to the transmitted signal from the companion IXBD4410. A "high" at INH of the IXBD4410 drives will turn it on ("high"). A "low" will turn it off ("low"). This output will turn off ("low") also in response to any fault condition.
VEE
T Connected to A Pin 14 (substrate) B
(c) 2004 IXYS All rights reserved
IXBD4410 IXBD4411
Application
The IXBD4410/4411 chipset devices are specifically designed as MOSgated transistor drivers in half-bridge power converters, 1- and 3-phase motor controls, and UPS applications. The phase-leg PWM command is normally generated by previous (user provided) circuitry. It must be decomposed into two separate logic signals, one for the high-side and one for the low-side power transistors, with appropriate deadtime for each state transition. The deadtime insures nonoverlapping conduction even if the turn-on and turn-off delay times of the power devices are unequal. The minimum deadtime should be greater than tdlh. A separate circuit, or an IC device like the IXYS deadtime generator IXDP630, can be used to perform this function. The ISOSMARTTM chipset family of devices do not generate deadtime, although there is an internal lockout that prohibits one device form being commanded "on" before the other is commanded "off". This simplifies startup and shutdown protection circuitry, preventing logic error during power-up from turning on both high-and low-side transistors simultaneously. Negative VEE Charge Pump Circuit Design The on-chip VEE generator provided in the IXBD4410/4411 generates a negative power supply, regulated at 20 V below the positive VDD rail. If VDD is +10 V, VEE will be -10 V. If VDD is +15 V, VEE will be -5 V. This negative drive potential in the off-state is either desirable or required in many instances. When switching a clamped inductive load (Fig. 5), the turn-on of Q2 will commutate the freewheeling diode around Q1. Whether this diode is intrinsic (as in a MOSFET) or extrinsic (IGBT or bipolar), its reverse recovery is critical to proper circuit operation. At high turn-on di/dt in Q2 and near its rated voltage, the recovery of D1 can get quite "snappy" (the di/dt in the second half of the recovery process, after the diode has begun to recover its blocking capability, can get very large), creating a very high dv/dt across Q1. This dv/dt is impressed across the Miller capacitance of Q1, forcing a large current to flow out the gate (c) 2004 IXYS All rights reserved
reduces the voltage required to create a failure, this problem is even more likely to occur. In an industrial module package (e.g.: a 150 A/1200 V IGBT phase-leg module), the series inductance contributed by the long gate leads and connectors further complicate the design. In a heavily snubbered converter, or in a power supply design with low transformer leakage inductance, the design problem is relatively simple and negative drive is seldom required. However, in a modern snubberless or lightly snubbered converter design, it is important to keep the gate drive impedance high enough during transistor turnoff to limit the reapplied dv/dt (the transistor is its own 'active' snubber). This is always important for EMI control, and in the case of IGBT may be required to achieve the necessary RBSOA. At the same time, it is mandatory to keep the off-state gate drive impedance very low to assure the transistor remain off during induced dv/dt (including diode recovery dv/dt). In some instances, it is simply not possible to satisfy both criteria with 0 V applied in the off-state. In these cases the IXBD4410/4411 with VEE negative bias generator must be used. The internal VEE generator is a charge pump circuit. Referring to Fig. 6, an external charge pump capacitor is required between the CA and CB
Fig. 5: Switching a clamped inductive load terminal of the device. If this current pulse causes a high enough voltage drop across the output impedance of the gate drive circuit, Rout, Q1 will be turned on. The Q1 conduction in every instance Q2 is turned on (and vice versa), aside from degrading efficiency, can lead to catastrophic failure of both power transistors. At high temperature, where the -6 to -7 mV/C temperature coefficient of IGBT/MOSFET threshold
1N5817
1N5817
Fig. 6: IXBD4410/4411 Detailed one phase circuit with dead time generator IXDP 630
7
IXBD4410 IXBD4411
terminals (C7, C11), and an output reservoir capacitor between VEE and GND (C10, C14). A 0.1 F charge pump capacitor (C7, C11) is recommended. The voltage regulation method used in the IXBD4410/4411 allows a 1 to 2 V ripple frequency depends on the size of the VEE output reservoir capacitor (C10, C14) and the average load current. The minimum recommended output reservoir (C10, C14) is 4.7 F tantalum, or 10 F if aluminium electrolytic construction is chosen. Note that this reservoir capacitor is in addition to a good quality high frequency bypass capacitor (0.1 F) that should be placed from VEE to GND (C9, C13). A small resistor in series with the charge pump capacitor, (R7, R8) reduces the peak charging currents of the charge pump. A value or 68 or greater is recommended, as illustrated in the applications example in Fig. 6. Current Sense / Desaturation Detection Circuit All members of the ISOSMARTTM driver family provide a very flexible overcurrent/short circuit protection capability that works with both standard three-terminal power transistors, and with 4- and 5-terminal current sensing power devices. Overcurrent detection is accomplished as illustrated in Fig. 7a (for a current mirror power device) and Fig. 7b (for a standard three terminal power transistor). Desaturation detection is accomplished with the same internal circuits by measuring the voltage across the power transistor in the on-state with an external resistor divider (Fig. 7c). The IM input trip point VTIM, typically 300 mV, is referenced to the Kelvin ground pin KG. Current Mirror MOSFET and IGBT allow good control of peak let-through currents and excellent short circuit protection when combined with the ISOSMARTTM driver family of devices. The sense resistor is chosen to develop 300 mV at the desired peak transistor current, assuming a mirror ration of 1400:1, and a trip point of 30 A is desired: Rs = 300 mV * 1400/30 A = 14 (use 15 CC). It is important to realize that Coss per a b c
IM
Rs
IM
Rs
IM
Rs
KG GND With Current Mirror
KG GND With Standard MOSFET/IGBT
KG GND Desaturation Detection with Standard MOSFET/IGBT
Fig. 7: Alternative overcurrent protection circuits unit area of the mirror cells is much larger that Coss per unit area of the bulk of the chip due to periphery effects. This causes a large transient current pulse at the mirror output whenever the transistor switches (C * dv/dt currents), which can cause false overcurrent trigger. The RC filter indicated in Fig. 7a will eliminate this problem. Standard three-terminal MOSFET and IGBT devices (in discrete as well as modern industrial single transistor and phase-leg modules) can also be protected from short circuit with the ISOSMARTTM driver family devices. In discrete device designs, where the source/emitter terminal is available, overcurrent protection with an external power resistor can be implemented. The resistor is placed in series with the device emitter, with the full device current flowing through it (Fig. 7b). The sense resistor is again selected to develop 300 mV at the desired peak transistor current, assuming a trip point of 30 A is desired: Rs = 300 mV / 30 A = 10 m (use 10 m, noninductive current sense resistor). It is important to recognize that "noninductive" is a relative term, especially when applied to current sense resistor construction and characterization. There is always significant series inductance inserted with the sense resistor, and L * di/dt voltage transients can cause false overcurrent trigger. The RC filter indicated in Figure 7b will eliminate this problem. Choosing the RC pole at the current sense resistor RL zero should exactly compensate for series inductance. Because the exact value is not normally known (and can vary depending on PC layout and component lead dress) this is not normally a good idea. Usually, the RC time constant should be two to ten times longer than the suspected RL time constant. Desaturation detection as in Figure 7c is probably the most common method of short circuit protection in use today. While not strictly an "overcurrent" detector, if the power transistor gain, and consequently short circuit letthrough current, is well controlled (as with modern MOSFET and IGBT) this methodology offers very effective protection. The IXBD4410/4411 half-bridge circuits in Fig. 6 uses desaturation detection. In Fig. 6, the voltage across the two power MOSFET devices (or IGBTs) are monitored by two sets of voltagedivider networks, R10 and R11 for the high-side gate driver, and R13 and R14 for the low-side gate driver. The dividers are set to trip the IM input comparators when either Power MOSFET device VDS exceeds a reasonable value, perhaps 50 V (usually a value of 10 % of the nominal DC bus voltage works well). R10 or R13 are chosen to tolerate the applied steady state DC bus voltage at an acceptable power dissipation. Dielectric withstand capability, power handling, temperature rise, and PC board creep and strike spacings, must all be carefully considered in the design of the voltage-divider networks. In the off-state, the voltage across the Power MOSFET device may go as high as the DC bus potential. To keep this normal condition from setting the internal fault flip-flop of the IXBD4410 or the IXBD4411, an internal CMOS switch is turned on and placed across lM and KG pins shorting them together. This effectively discharges C8 or C12 in Fig. 6 and maintains zero potential (c) 2004 IXYS All rights reserved
IXBD4410 IXBD4411
with respect to KG at IM. When the command arrives to switch on the Power MOSFET device, the CMOS switch shorting IM to KG is turned off. The driven Power MOSFET device is switched on approximately 100 ns to 1 s later, and with typical load conditions, its drain-to-source potential, VDS, may take an additional 10 s of delay to collapse to the normal on-state voltage level. To prevent false triggering due to this, C8 or C12 in parallel combination with R10 and R11, or R13 and R14, delays the IM input signal. During this turn-on interval, the voltage across C8 or C12 will rise until the Power MOSFET device finally comes on and pulls the voltage across C8 or C12 back down. If the MOSFET device load circuit is shorted, its VDS voltage cannot collapse at turn-on. In this case, the voltage across C8 or C12 rises rapidly until it reaches 300 mV, tripping the fault flip-flop and shutting down the driver output. At the same time, C8 or C12 must be kept small enough that the added delay does not slow down the detection of a short circuit event so much that the Power MOSFET device fails before the driver realizes that it is in trouble. Three Phase Motor Controls Fig. 8 is a block diagram of a typical 3phase PWM voltage-source inverter motor control. The power circuit consists of six power switching transistors with freewheeling diodes around each of them. The control function may be performed digitally by a microprocessor, microcontroller, DSP chip, or user custom IC; or it may be performed by a PC board full of random logic and analog circuits. In any of these cases, the PWM command for all six power transistors is generated in one circuit, and this circuit is usually referred to system ground potential - the bottom terminal of the power bridge. The ISOSMARTTM family of drivers is the interface between the world of control logic and the world of power, 5 V input logic commands precisely control actions at high voltage and current (1200 V and 100 A in a typical application). Fig. 6 is a detailed schematic of one phase of three 3-phase motor control, showing the interconnection of the IXBD4410/4411 and its associated circuitry.
Fig. 8: Typical 3-phase motor control system block diagram PCB Layout Considerations The IXBD4410/4411 is intended to be used in high voltage, high speed, high dv/dt applications. To ensure proper operation, great care must be taken in laying out the printed circuit board. The layout critical areas include the communication links, current sense, gate drive, and supply bypassing. The communication path should be as short as possible. Added inductance disturbs the frequency response of the signal path, and these distortions may cause false triggering in the receiver. The transformer should be placed between the two ICs with the orientation of one IC reversed (Fig. 9). Capacitance between the high- and lowside should be minimized. No signal trace should run underneath the communication path, and high- and lowside traces should be separated on the PCB. The dv/dt of the high-side during power stage switching may cause false logic transitions in low-side circuits due to capacitive coupling. The low signal pulse transformer provides the isolation between high-and low-side circuits. For 460 V~ line operation, a spacing of 4 mm is recommended between low- and high-side circuits, and a transformer HIPOT specification of at least 1500 V~ is required. This creep spacing is usually adequate to control leakage currents on the PCB with up to 1200 V~ applied after 10 to 15 years of accumulated dust and particulates in a standard industrial environment. In other environments, or at other line voltages, this spacing should be appropriately modified. The current sense/desaturation detect input is noise sensitive. The 300 mV trip point is referred to the KG (Kelvin ground) pin, and the applied signal must be kept as clean as possible, A filter is recommended, preferably a monolithic ceramic capacitor placed as close to the IC as possible directly between IM and KG. To preserve maximum noise immunity, the KG pin should first be connected directly to the LG pin, and the pair then sent directly to the power transistor source/emitter terminal, or (if a desaturation detection circuit is used) to the bottom of the divider resistor chain. All supply pins must be bypassed with a low impedance capacitor (preferably monolithic ceramic construction) with minimum lead length. The output driver stage draws 2 A (typical) currents during transitions at di/dt values in excess of 100 A/s. Supply line inductance will cause supply and ground bounce on the chip that can cause problems (logic oscillations and, in severe cases, possible latch-up failure) without proper bypassing. These bypass elements are in addition to the reservoir capacitors required for the negative Vee supply and the high-side bootstrapped supply if these features are used. Power Circuit Noise Considerations In a typical transistor inverter, the output MOSFET may switch on or off with di/dt >500 A/s. Referring to Fig.10 and assuming that the MOSFET source terminal has a one inch path on the PCB to system ground, a voltage as high as V = 27 nH * 500 A/s = 13.5 V can be developed.
(c) 2004 IXYS All rights reserved
9
IXBD4410 IXBD4411
If the MOSFET switched 25 A, the transient will last as long as (25/500) s or 50 ns, which is more than the typical 6 or 7 ns propagations or of a 74HC series gate. Fig. 10 illustrates an example layout problem. The power circuit consists of three power transistors (MOSFETs in this example). With the ISOSMARTTM gate driver chipset grounded as in option (b) in Fig. 10, the communication path from the IXDP630 will operate without errors. The PC trace induced voltages are not common with the digital drive output follows (after its propagation delay) and the MOSFET starts to conduct. The voltage transient induced across LS1 (V = LS1 * di/dt) raises the local ground (point a) until it exceeds Voh (630) - Vil and the driver (after its propagation delay) turns the MOSFET off. Now the MOSFET current falls, V(LS1) drops, point (a) drops to system ground (or slightly below), and the driver detects a "1" at its input. After its propagation delay, it again turns the conversion equipment due to their very high common mode dv/dt rejection capabilities. Transformer Considerations The transformer is the communication link and isolation barrier between the high- and low-side ICs. The high-side gate and fault signals are transmitted through the transformer while maintaining the proper isolation. The transmitter signal is in the form of a
Fig. 9: Suggested IC Orientation path, so the input of the gate driver will not see or respond to them. Unfortunately, the MOSFET will not operate properly. The voltage induced across LS1 when Q1 is turned on, acts as source degeneration, modifying the turn-on behavior of the MOSFET. If LS1= 27 nH, and VCC is 15 V (assuming the gate plateau of the MOSFET is 6 V), the di/dt at turn-on will be regulated by the driver/MOSFET/LS1 loop to about 200 A/s; quite a surprise when your circuit requires 500 A/s to operate correctly. It is possible to make use of this behavior to create a turn-on or turn-off di/dt limiter (perhaps to snub the upper free wheeling diode reverse recovery). While possible, this is normally not desirable or practical where two or more transistors are controlled. Equalizing the parasitic impedances of three traces while positioning the transistors next to their heat sink and meeting UL/VDE voltage spacings is just too difficult. Grounding the gate driver as in option (a) in Fig. 10 solves the MOSFET turn on problem by eliminating LS1 from the source feedback loop. Now, unfortunately, the gate driver will oscillate every time it is turned on or off. As the IXDP630 output goes "high", the gate
Fig. 10: Potential layout problems that create functional problems MOSFET on, continuing the oscillation for one more cycle. To eliminate this problem, a ground level transformation circuit must be added, that rejects this common mode transient. The simplest is a de-coupling circuit, also illustrated in Fig. 10. The capacitor voltage on Cd remains constant while the transient voltage is dropped across Rd and the driver detects no input transition, eliminating the oscillation. This circuit does add significantly to turn-on and turn-off delay time, and cannot be used if the transient lasts longer than the allowable delays. Delay times must be considered in selection of system dead time. The most complex (and most effective) method of eliminating the effects of transients between grounds is isolation. Optocouplers and pulse transformers are the most commonly used isolation techniques, and work very well in this case. The IXDP630/631 has been specifically designed to directly drive a high speed optocoupler like the Hewlett Packard HCPL22XX family or the General Instrument 740L60XX optologic family. These optos are especially well suited to motor control and power square wave, but the receiver responds only to the logic edges. This allows for much smaller transformer designs, since a 10 kHz switching frequency does not require a 10 kHz pulse transformer. The recommended transformer for this ISOSMARTTM driver chipset is fabricated using a very small ferrite shield bead (see Fig. 11), onto which a six-turn primary and a two-turn secondary winding of 36 AWG magnet wire are made. The two windings are segment wound to achieve primary-tosecondary isolation of up to 2500 V~. The six-turn primaries are connected to the respective IXBD4410/4411 transmitter outputs and the two-turn secondaries are connected to their respective receiver inputs.
(c) 2004 IXYS All rights reserved
IXBD4410 IXBD4411
The nominal electrical specifications of the transformer are as follows: Open circuit inductance (100 kHz; 20 mV): 3 H Interwinding capacitance: 2 pF Primary leakage inductance: 0.1 H Turns ratio: 6:2 Primary-to-secondary isolation (1min): 1500 V~ Core permeability (i): 125 The recommended ferrite bead is Fair Rite Products part number 2661000101, which is manufactured by: Fair-Rite Products Corp. Wallkill, NY Phone: (800) 836-0427 Web site: www.fair-rite.com As seen in the application drawings (Fig. 6, 9 and 12) a coupling capacitor (22 nF) and a damping resistor (22 ) are added in series with the primary side of the transformer. The capacitor will control the small amount of energy needed to transfer the signal to the companion driver. The resistor will control the damping of the signal and limit the peak transmitter output current. The receiver is designed to operate
Fig. 11: Ferrite bead dimensions over a wide common mode input range. To reduce noise pickup, the receiver has 250 mV of input hysteresis. If the signal is being distorted at the transmitter, the transmitter is probably running into current limit. A decrease in the coupling capacitance or an increase in the damping resistance should solve this problem. The receiver operates over a wide input range. The minimum amplitude for one side of the receiver is about 1 V and a maximum of about 3 V. It is critical that there be no overshoot on the transformer secondary waveform. Each signal should be slightly overdamped. If significant overshoot exists, the received signal may be logically inverted. An increase of the damping resistor will solve this problem.
Fig. 12: Transmitter/Receiver Waveforms
DS96528E(05/04)
(c) 2004 IXYS All rights reserved
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